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rev.2.00, oct.02. 2003, page 1 of 12 HD74ALVCH16269 12-bit to 24-bit registered bus transceivers with 3-state outputs rej03d0046-0200z (previous ade-205-136(z)) rev.2.00 oct.02.2003 description the HD74ALVCH16269 is used in applications wher e two separate ports must be multiplexed onto, or demultiplexed from, a single port. the device is par ticularly suitable as an interface between synchronous drams and high speed microprocessors. data is stored in the internal b port registers on the low to high transition of the clock (clk) input when the appropriate clock enable ( clkena ) inputs are low. proper control of these inputs allows two sequential 12-bit wo rds to be presented as a 24-bit word on the b port. for data transfer in the b to a direction, a sing le storage register is provided. the select ( sel ) line selects 1b or 2b data for the a outputs. the register on the a output permits the fastest possible data transfer, thus extending the period that the data is valid on the bus. the control terminals are registered so that all transactions are synchronous with clk. data fl ow is controlled by the active low output enables ( oea , oeb1 , oeb2 ). active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. features ? v cc = 2.3 v to 3.6 v ? typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) ? typical v oh undershoot > 2.0 v (@v cc = 3.3 v, ta = 25c) ? high output current 24 ma (@v cc = 3.0 v) ? bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 2 of 12 function table inputs outputs clk oea oeb a1 b , 2 b hhz z h l z active l h active z l l active active output enable inputs outputs clkena1 clkena2 clk a 1b 2b hhxx1 b 0 *1 2b 0 *1 lx ll x lx hh x xl lx l xl hx h a-to-b storage ( oeb = l) inputs output a clk sel 1b 2b xhxx a 0 *1 xlxx a 0 *1 hl x l hhx h lxl l lxh h b-to-a storage ( oea = l) h : high level l : low level x : immaterial z : high impedance : low to high transition note: 1. output level before the indicated stea dy state input conditio ns were established.
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 3 of 12 pin arrangement (top view) 1 2 3 4 5 6 7 8 9 10 v cc v cc o eb1 2b3 gnd 2b2 2b1 a1 a2 a3 gnd a4 a5 a6 a7 a8 a9 gnd a10 a11 a12 1b1 1b2 oea 11 12 13 14 15 16 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1b5 gnd 25 32 gnd 1b3 26 31 1b4 nc 27 30 clkena 1 sel 28 29 clk 1b6 1b7 1b8 1b9 1b10 gnd 1b11 1b12 2b12 2b11 2b10 gnd 2b9 2b8 2b7 2b6 2b5 2b4 oeb2 gnd clkena 2 v cc v cc
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 4 of 12 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc ?0.5 to 4.6 v input voltage *1, 2 v i ?0.5 to 4.6 v except i/o ports ?0.5 to v cc +0.5 i/o ports output voltage *1, 2 v o ?0.5 to v cc +0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 50 ma v o = 0 to v cc 100 maximum power dissipation at ta = 55c (in still air) *3 p t 1w t s s o p storage temperature tstg ?65 to 150 c notes: stresses beyond those listed under ?absolut e maximum ratings? may cause permanent damage to the device. these are stress ratings only, and f unctional operation of t he device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. this value is limited to 4.6 v maximum. 3. the maximum package power dissipation is calculated using a junction temperature of 150c and a board trace length of 750 mils. recommended operating conditions item symbol min max unit conditions supply voltage v cc 2.3 3.6 v input voltage v i 0v cc v output voltage v o 0v cc v ? ?12 v cc = 2.3 v ? ?12 v cc = 2.7 v high level output current i oh ? ?24 ma v cc = 3.0 v ?1 2 v cc = 2.3 v ?1 2 v cc = 2.7 v low level output current i ol ?2 4 ma v cc = 3.0 v input transition rise or fall rate ? t / ? v 0 10 ns / v operating temperature ta ?40 85 c note: unused control inputs must be held hi gh or low to prevent them from floating.
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 5 of 12 logic diagram 1 of 12 channels 1d c1 1d c1 1d c1 1d ce c1 1d ce c1 1d c1 1d c1 clk oeb1 oeb2 clkena1 sel oea a1 1b1 2b1 clkena2 g1 1 1 29 2 56 23 6 30 55 28 1 8
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 6 of 12 electrical characteristics (ta = ?40 to 85c) item symbol v cc (v) *1 min max unit test conditions 2.3 to 2.7 1.7 ? v ih 2.7 to 3.6 2.0 ? 2.3 to 2.7 ? 0.7 input voltage v il 2.7 to 3.6 ? 0.8 v min to max v cc ?0.2 ? i oh = ?100 a 2.3 2.0 ? i oh = ?6 ma, v ih = 1.7 v 2.3 1.7 ? i oh = ?12 ma, v ih = 1.7 v 2.7 2.2 ? i oh = ?12 ma, v ih = 2.0 v 3.0 2.4 ? i oh = ?12 ma, v ih = 2.0 v v oh 3.0 2.0 ? i oh = ?24 ma, v ih = 2.0 v min to max ? 0.2 i ol = 100 a 2.3 ? 0.4 i ol = 6 ma, v il = 0.7 v 2.3 ? 0.7 i ol = 12 ma, v il = 0.7 v 2.7 ? 0.4 i ol = 12 ma, v il = 0.8 v output voltage v ol 3.0 ? 0.55 v i ol = 24 ma, v il = 0.8 v i in 3.6 ? 5 v in = v cc or gnd 2.3 45 ? v in = 0.7 v 2.3 ?45 ? v in = 1.7 v 3.0 75 ? v in = 0.8 v 3.0 ?75 ? v in = 2.0 v input current i in (hold) 3.6 ? 500 a v in = 0 to 3.6 v off state output current *2 i oz 3.6 ? 10 av out = v cc or gnd i cc 3.6 ? 40 av in = v cc or gnd quiescent supply current ? i cc 3.0 to 3.6 ? 750 av in = one input at (v cc ?0.6) , other inputs at v cc or gnd notes: 1. for conditions shown as min or max, use the appropriate values under recommended operating conditions. 2. for i/o ports, the parameter i oz includes the input leakage current.
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 7 of 12 switching characteristics item symbol v cc (v) min typ max unit from (input) to (output) 2.50.2 135 ? ? 2.7 135 ? ? maximum clock frequency f max 3.30.3 135 ? ? mhz 2.50.2 1.0 ? 8.8 2.7??7.3 3.30.3 1.0 ? 6.2 b 2.50.2 1.0 ? 7.0 2.7??5.8 propagation delay time t plh t phl 3.30.3 1.0 ? 5.0 ns clk a 2.50.2 1.0 ? 8.4 2.7??6.7 3.30.3 1.0 ? 6.1 b 2.50.2 1.0 ? 8.1 2.7??6.2 output enable time t zh t zl 3.30.3 1.0 ? 5.9 ns clk a 2.50.2 1.4 ? 8.3 2.7??6.9 3.30.3 1.0 ? 6.1 b 2.50.2 1.5 ? 7.7 2.7??6.8 output disable time t hz t lz 3.30.3 1.0 ? 5.6 ns clk a input capacitance c in 3.3 ? 3.5 ? pf control inputs output capacitance c in / o 3.3 ? 9.0 ? pf a or b ports
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 8 of 12 switching characteristics (cont.) item symbol v cc (v) min typ max unit from (input) 2.50.2 2.0 ? ? 2.7 2.0 ? ? 3.30.3 1.7 ? ? a data before clk 2.50.2 2.2 ? ? 2.7 2.1 ? ? 3.30.3 1.8 ? ? b data before clk 2.50.2 1.6 ? ? 2.7 1.6 ? ? 3.30.3 1.3 ? ? sel before clk 2.50.2 1.0 ? ? clkena1 or 2.7 1.2 ? ? 3.30.3 0.9 ? ? clkena2 before lk 2.50.2 1.5 ? ? 2.7 1.6 ? ? setup time t su 3.30.3 1.3 ? ? ns oe before clk 2.50.2 0.7 ? ? 2.7 0.6 ? ? 3.30.3 0.6 ? ? a data after clk 2.50.2 0.7 ? ? 2.7 0.6 ? ? 3.30.3 0.6 ? ? b data after clk 2.50.2 1.1 ? ? 2.7 0.7 ? ? 3.30.3 0.7 ? ? sel aftrer clk 2.50.2 1.0 ? ? clkena1 or 2.7 0.8 ? ? 3.30.3 1.1 ? ? clkena2 after clk 2.50.2 0.8 ? ? 2.7 0.8 ? ? hold time t h 3.30.3 0.8 ? ? ns oe after clk 2.50.2 3.3 ? ? 2.7 3.3 ? ? pulse width t w 3.30.3 3.3 ? ? ns clk ?h? or ?l?
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 9 of 12 500 ? c = 50 pf l l 500 ? s1 *1 see under table gnd open load circuit for outputs note: 1. c includes probe and jig capacitance. symbol t / t plh phl open gnd 4.6 v 6.0 v t / t zh hz t / t zl lz t / t / t su h w open gnd vcc=2.7v, 3.30.3v vcc=2.50.2v test circuit
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 10 of 12 t plh t phl t su t h v oh v ol t w gnd v ih gnd v ih gnd v ih gnd v ih v ref v ref v ref v ref v ref v ref v ref v ref v ref input output timing input data input input waveforms ? 1 waveforms ? 2 10 % 90 % tr tf 10 % 90 % 10 % 90 % tr
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 11 of 12 v ? 0.3 v oh v + 0.3 v ol t zl t lz t zh t hz v oh v ol waveform - a output control waveform - b gnd v ih v ol1 v oh1 v ref v ref v ref v ref test v ih v ref v oh1 v ol1 1.2 v 1.5 v 2.3 v 3.0 v gnd 2.3 v 2.7 v gnd vcc=2.7v, 3.30.3v vcc=2.50.2v notes: 1. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, zo = 50 ?, tr 2.5 ns, tf 2.5 ns. 2. waveform ? a is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform ? b is for an output with internal conditions such that the output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement. waveforms ? 3 tr tf 10 % 10 % 90 % 90 %
HD74ALVCH16269 rev.2.00, oct.02. 2003, page 12 of 12 package dimensions package code jedec jeita mass (reference value) ttp-48/40da ? ? 0.60 g *dimension including the plating thickness base material dimension 0.13 0.80 m 0.10 19.68 20.00 max 12.70 48 39 34 1101524 25 0.94 max 1.20 max 4.00 0.05 0.05 14.30 0.20 0.32 0.10 0.30 0.05 * 0.145 0.05 0.125 0.04 * 0? ? 5? 0.50 0.10 0.78 0.80 as of january, 2003 unit: mm
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